Implementing the Log-Add Algorithm in Hardware

Stephen Melnikoff; Steven Quigley

doi:10.1049/el:20030594

Implementing the Log-Add Algorithm in Hardware

Stephen Melnikoff, Steven Quigley

Electronic, Electrical and Systems Engineering

Research output: Contribution to journal › Letter › peer-review

10 Citations (Scopus)

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Abstract

A hardware implementation of the log-add algorithm, being a simple method of computing ln(A + B) given ln(A) and ln(B), as used in speech recognition, is presented. It is shown that it can be efficiently implemented in hardware using a small look-up table plus some additional arithmetic logic, with no significant loss of accuracy over direct calculation.

Original language	English
Pages (from-to)	939-941
Number of pages	3
Journal	Electronics Letters
Volume	39
Issue number	12
DOIs	https://doi.org/10.1049/el:20030594
Publication status	Published - 1 Jan 2003

Bibliographical note

null

This paper is a postprint of a letter submitted to and accepted for publication in Electronics Letters and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.

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Melnikoff03ELLetteroriginal.pdf
Institution of Engineering and Technology
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http://ieeexplore.ieee.org/iel5/2220/27211/01209507.pdf?isnumber=&arnumber=1209507

Cite this

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Implementing the Log-Add Algorithm in Hardware

Abstract

Bibliographical note

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