Implementing the Log-Add Algorithm in Hardware

Research output: Contribution to journalLetter


Colleges, School and Institutes


A hardware implementation of the log-add algorithm, being a simple method of computing ln(A + B) given ln(A) and ln(B), as used in speech recognition, is presented. It is shown that it can be efficiently implemented in hardware using a small look-up table plus some additional arithmetic logic, with no significant loss of accuracy over direct calculation.

Bibliographic note

null This paper is a postprint of a letter submitted to and accepted for publication in Electronics Letters and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.


Original languageEnglish
Pages (from-to)939-941
Number of pages3
JournalElectronics Letters
Issue number12
Publication statusPublished - 1 Jan 2003