Physical security evaluation of the bitstream encryption mechanism of altera stratix II and stratix III FPGAs

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Physical security evaluation of the bitstream encryption mechanism of altera stratix II and stratix III FPGAs. / Swierczynski, Pawel; Moradi, Amir; Oswald, David; Paar, Christof.

In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 7, No. 4, 34, 01.12.2014.

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@article{27ff9d26d26d4b8db4d66dff1533ca62,
title = "Physical security evaluation of the bitstream encryption mechanism of altera stratix II and stratix III FPGAs",
abstract = "To protect Field-Programmable Gate Array (FPGA) designs against Intellectual Property (IP) theft and related issues such as product cloning, all major FPGA manufacturers offer a mechanism to encrypt the bitstream that is used to configure the FPGA. From a mathematical point of view, the employed encryption algorithms (e.g., Advanced Encryption Standard (AES) or 3DES) are highly secure. However, it has been shown that the bitstream encryption feature of several FPGA families is susceptible to side-channel attacks based on measuring the power consumption of the cryptographic module. In this article, we present the first successful attack on the bitstream encryption of the Altera Stratix II and Stratix III FPGA families. To this end, we analyzed the Quartus II software and reverse engineered the details of the proprietary and unpublished schemes used for bitstream encryption on Stratix II and Stratix III. Using this knowledge, we demonstrate that the full 128-bit AES key of a Stratix II as well as the full 256-bit AES key of a Stratix III can be recovered by means of side-channel attacks. In both cases, the attack can be conducted in a few hours. The complete bitstream of these FPGAs that are (seemingly) protected by the bitstream encryption feature can hence fall into the hands of a competitor or criminal-possibly implying system-wide damage if confidential information such as proprietary encryption schemes or secret keys programmed into the FPGA are extracted. In addition to lost IP, reprogramming the attacked FPGA with modified code, for instance, to secretly plant a hardware Trojan, is a particularly dangerous scenario formany security-critical applications.",
keywords = "AES, Altera, Bitstream encryption, Hardware security, Reverse engineering, Side-channel attack, Stratix II, Stratix III",
author = "Pawel Swierczynski and Amir Moradi and David Oswald and Christof Paar",
year = "2014",
month = "12",
day = "1",
doi = "10.1145/2629462",
language = "English",
volume = "7",
journal = "ACM Transactions on Reconfigurable Technology and Systems",
issn = "1936-7406",
publisher = "Association for Computing Machinery",
number = "4",

}

RIS

TY - JOUR

T1 - Physical security evaluation of the bitstream encryption mechanism of altera stratix II and stratix III FPGAs

AU - Swierczynski, Pawel

AU - Moradi, Amir

AU - Oswald, David

AU - Paar, Christof

PY - 2014/12/1

Y1 - 2014/12/1

N2 - To protect Field-Programmable Gate Array (FPGA) designs against Intellectual Property (IP) theft and related issues such as product cloning, all major FPGA manufacturers offer a mechanism to encrypt the bitstream that is used to configure the FPGA. From a mathematical point of view, the employed encryption algorithms (e.g., Advanced Encryption Standard (AES) or 3DES) are highly secure. However, it has been shown that the bitstream encryption feature of several FPGA families is susceptible to side-channel attacks based on measuring the power consumption of the cryptographic module. In this article, we present the first successful attack on the bitstream encryption of the Altera Stratix II and Stratix III FPGA families. To this end, we analyzed the Quartus II software and reverse engineered the details of the proprietary and unpublished schemes used for bitstream encryption on Stratix II and Stratix III. Using this knowledge, we demonstrate that the full 128-bit AES key of a Stratix II as well as the full 256-bit AES key of a Stratix III can be recovered by means of side-channel attacks. In both cases, the attack can be conducted in a few hours. The complete bitstream of these FPGAs that are (seemingly) protected by the bitstream encryption feature can hence fall into the hands of a competitor or criminal-possibly implying system-wide damage if confidential information such as proprietary encryption schemes or secret keys programmed into the FPGA are extracted. In addition to lost IP, reprogramming the attacked FPGA with modified code, for instance, to secretly plant a hardware Trojan, is a particularly dangerous scenario formany security-critical applications.

AB - To protect Field-Programmable Gate Array (FPGA) designs against Intellectual Property (IP) theft and related issues such as product cloning, all major FPGA manufacturers offer a mechanism to encrypt the bitstream that is used to configure the FPGA. From a mathematical point of view, the employed encryption algorithms (e.g., Advanced Encryption Standard (AES) or 3DES) are highly secure. However, it has been shown that the bitstream encryption feature of several FPGA families is susceptible to side-channel attacks based on measuring the power consumption of the cryptographic module. In this article, we present the first successful attack on the bitstream encryption of the Altera Stratix II and Stratix III FPGA families. To this end, we analyzed the Quartus II software and reverse engineered the details of the proprietary and unpublished schemes used for bitstream encryption on Stratix II and Stratix III. Using this knowledge, we demonstrate that the full 128-bit AES key of a Stratix II as well as the full 256-bit AES key of a Stratix III can be recovered by means of side-channel attacks. In both cases, the attack can be conducted in a few hours. The complete bitstream of these FPGAs that are (seemingly) protected by the bitstream encryption feature can hence fall into the hands of a competitor or criminal-possibly implying system-wide damage if confidential information such as proprietary encryption schemes or secret keys programmed into the FPGA are extracted. In addition to lost IP, reprogramming the attacked FPGA with modified code, for instance, to secretly plant a hardware Trojan, is a particularly dangerous scenario formany security-critical applications.

KW - AES

KW - Altera

KW - Bitstream encryption

KW - Hardware security

KW - Reverse engineering

KW - Side-channel attack

KW - Stratix II

KW - Stratix III

UR - http://www.scopus.com/inward/record.url?scp=84919608503&partnerID=8YFLogxK

U2 - 10.1145/2629462

DO - 10.1145/2629462

M3 - Article

VL - 7

JO - ACM Transactions on Reconfigurable Technology and Systems

JF - ACM Transactions on Reconfigurable Technology and Systems

SN - 1936-7406

IS - 4

M1 - 34

ER -