Performance of a Second Order Electrostatic Particle-in-Cell Algorithm on Modern Many-Core Architectures

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Authors

Colleges, School and Institutes

External organisations

  • University of Warwick

Abstract

In this paper we present the outline of a novel electrostatic, second order Particle-in-Cell (PIC) algorithm, that makes use of ‘ghost particles’ located around true particle positions in order to represent a charge distribution. We implement our algorithm within EMPIRE-PIC, a PIC code developed at Sandia National Laboratories. We test the performance of our algorithm on a variety of many-core architectures including NVIDIA GPUs, conventional CPUs, and Intel's Knights Landing. Our preliminary results show the viability of second order methods for PIC applications on these architectures when compared to previous generations of many-core hardware. Specifically, we see an order of magnitude improvement in performance for second order methods between the Tesla K20 and Tesla P100 GPU devices, despite only a 4× improvement in the theoretical peak performance between the devices. Although these initial results show a large increase in runtime over first order methods, we hope to be able to show improved scaling behaviour and increased simulation accuracy in the future.

Bibliographic note

Funding Information: This work was supported by the UK Atomic Weapons Establishment (AWE) under grant CDK0724 (AWE Technical Outreach Programme). Professor Stephen Jarvis is an AWE William Penney Fellow. Publisher Copyright: © 2018

Details

Original languageEnglish
Pages (from-to)67-84
Number of pages18
JournalElectronic Notes in Theoretical Computer Science
Volume340
Publication statusPublished - 29 Oct 2018

Keywords

  • Broadwell, GPU, K20, KNL, Many-Core, P100, Particle-in-Cell, PIC, Second Order Algorithms