Optimized Polynomial Multiplier Architectures for Post-Quantum KEM Saber

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Authors

Colleges, School and Institutes

Abstract

Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.

Details

Original languageEnglish
Title of host publicationDesign Automation Conference
Publication statusAccepted/In press - 25 Feb 2021
EventDesign Automation Conference - San Francisco, United States
Duration: 5 Dec 20219 Dec 2021
Conference number: 58
https://www.dac.com/

Conference

ConferenceDesign Automation Conference
Abbreviated titleDAC
CountryUnited States
CitySan Francisco
Period5/12/219/12/21
Internet address