Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Colleges, School and Institutes


Performing Viterbi decoding for continuous real-time speech recognition is a highly computationally-demanding task, but is one which can take good advantage of a parallel processing architecture. To this end, we describe a system which uses an FPGA for the decoding and a PC for pre- and post-processing, taking advantage of the properties of this kind of programmable logic device, specifically its ability to perform in parallel the large number of additions and comparisons required. We compare the performance of the FPGA decoder to a software equivalent, and discuss issues related to this implementation.

Bibliographic note

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Original languageEnglish
Title of host publication Field-Programmable Logic and Applications, 11th International Conference, FPL 2001. Proceedings
Publication statusPublished - 1 Jan 2001
EventInternational Conference on Field-Programmable Logic and Applications -
Duration: 1 Jan 2001 → …

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Verlag
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


ConferenceInternational Conference on Field-Programmable Logic and Applications
Period1/01/01 → …