Fully parallel implementation of Otsu automatic image thresholding algorithm on FPGA

Research output: Contribution to journalArticlepeer-review

Authors

Colleges, School and Institutes

External organisations

  • Federal University of Rio Grande Do Norte

Abstract

This work proposes a high-throughput implementation of the Otsu automatic image thresholding algorithm on Field Programmable Gate Array (FPGA), aiming to process high-resolution images in real-time. The Otsu method is a widely used global thresholding algorithm to define an optimal threshold between two classes. However, this technique has a high computational cost, making it difficult to use in real-time applications. Thus, this paper proposes a hardware design exploiting parallelization to optimize the system’s processing time. The implementation details and an analysis of the synthesis results concerning the hardware area occupation, throughput, and dynamic power consumption, are presented. Results have shown that the proposed hardware achieved a high speedup compared to similar works in the literature.

Details

Original languageEnglish
Article number4151
Number of pages17
JournalSensors
Volume21
Issue number12
Publication statusPublished - 17 Jun 2021

Keywords

  • FPGA, Image segmentation, thresholding algorithm, Otsu's method