FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Authors

  • Sujoy Sinha Roy
  • Furkan Turan
  • Kimmo Jarvinen
  • Frederik Vercauteren
  • Ingrid Verbauwhede

Colleges, School and Institutes

External organisations

  • KU Leuven, imec-COSIC, Belgium
  • University of Helskinki

Abstract

Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.

Details

Original languageEnglish
Title of host publication2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)
Publication statusPublished - 28 Mar 2019
Event25th IEEE International Symposium on High Performance Computer Architecture (HPCA 2019) - Washington, DC, United States
Duration: 16 Feb 201920 Feb 2019

Publication series

NameHigh-Performance Computer Architecture, IEEE Symposium on
PublisherIEEE
ISSN (Print)1530-0897
ISSN (Electronic)2378-203X

Conference

Conference25th IEEE International Symposium on High Performance Computer Architecture (HPCA 2019)
CountryUnited States
CityWashington, DC
Period16/02/1920/02/19

Keywords

  • cloud computing, privacy in cloud computing, homomorphic, encryption, FV homomorphic encryption, lattice-based cryptography, polynomial multiplication, number theoretic transform, domain specific accelerator, hardware accelerator