TY - GEN
T1 - FPGA-based high-performance parallel architecture for homomorphic computing on encrypted data
AU - Sinha Roy, Sujoy
AU - Turan, Furkan
AU - Jarvinen, Kimmo
AU - Vercauteren, Frederik
AU - Verbauwhede, Ingrid
PY - 2019/3/28
Y1 - 2019/3/28
N2 - Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.
AB - Homomorphic encryption is a tool that enables computation on encrypted data and thus has applications in privacy-preserving cloud computing. Though conceptually amazing, implementation of homomorphic encryption is very challenging and typically software implementations on general purpose computers are extremely slow. In this paper we present our year long effort to design a domain specific architecture in a heterogeneous Arm+FPGA platform to accelerate homomorphic computing on encrypted data. We design a custom co-processor for the computationally expensive operations of the well-known Fan-Vercauteren (FV) homomorphic encryption scheme on the FPGA, and make the Arm processor a server for executing different homomorphic applications in the cloud, using this FPGA-based co-processor. We use the most recent arithmetic and algorithmic optimization techniques and perform design-space exploration on different levels of the implementation hierarchy. In particular we apply circuit-level and block-level pipeline strategies to boost the clock frequency and increase the throughput respectively. To reduce computation latency, we use parallel processing at all levels. Starting from the highly optimized building blocks, we gradually build our multi-core multi-processor architecture for computing. We implemented and tested our optimized domain specific programmable architecture on a single Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. At 200 MHz FPGA-clock, our implementation achieves over 13x speedup with respect to a highly optimized software implementation of the FV homomorphic encryption scheme on an Intel i5 processor running at 1.8 GHz.
KW - cloud computing
KW - privacy in cloud computing
KW - homomorphic
KW - encryption
KW - FV homomorphic encryption
KW - lattice-based cryptography
KW - polynomial multiplication
KW - number theoretic transform
KW - domain specific accelerator
KW - hardware accelerator
UR - http://www.scopus.com/inward/record.url?scp=85064190897&partnerID=8YFLogxK
U2 - 10.1109/HPCA.2019.00052
DO - 10.1109/HPCA.2019.00052
M3 - Conference contribution
T3 - High-Performance Computer Architecture, IEEE Symposium on
SP - 387
EP - 398
BT - 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)
PB - IEEE Computer Society Press
T2 - 25th IEEE International Symposium on High Performance Computer Architecture (HPCA 2019)
Y2 - 16 February 2019 through 20 February 2019
ER -