Defect- and Variation-tolerant Logic Mapping in Nano-crossbar Using Bipartite Matching and Memetic Algorithm

Research output: Contribution to journalArticle

Authors

Colleges, School and Institutes

External organisations

  • University of Science and Technology of China, Hefei, China

Abstract

High defect density and extreme parameter variation make it very difficult to implement reliable logic functions in crossbar-based nanoarchitectures. It is a major design challenge to tolerate defects and variations simultaneously for such architectures. In this paper, a method based on a bipartite matching and memetic algorithm is proposed for defect- and variation-tolerant logic mapping (D/VTLM) problem in crossbar-based nanoarchitectures. In the proposed method, the search space of the D/VTLM problem can be dramatically reduced through the introduction of the min-max weight maximum-bipartite-matching (MMW-MBM) and a related heuristic bipartite matching method. MMW-MBM is defined on a weighted bipartite graph as an MBM, where the maximal weight of the edges in the matching has a minimal value. In addition, a defect- and variation-aware local search (D/VALS) operator is proposed for D/VTLM and embedded in a global search framework. The D/VALS operator is able to utilize the domain knowledge extracted from problem instances and, thus, has the potential to search the solution space more efficiently. Compared with the state-of-the-art heuristic and recursive algorithms, and a simulated annealing algorithm, the good performance of our proposed method is verified on a 3-bit adder and a large set of random benchmarks of various scales.

Details

Original languageEnglish
Pages (from-to)2813-2826
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number9
Early online date3 Mar 2016
Publication statusPublished - 23 Aug 2016