A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

Research output: Contribution to journalArticle

Authors

Colleges, School and Institutes

Abstract

This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results.

Details

Original languageEnglish
Pages (from-to)207-215
Number of pages9
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume31
Early online date13 Mar 2015
Publication statusPublished - Apr 2015

Keywords

  • Built-In Self-Test, Field-Programmable Gate Array, Global Interconnection Resource Testing, FPGA Testing and Diagnosis