TY - GEN
T1 - Solution of the three-dimensional finite difference equations using parallel reconfigurable hardware accelerators
AU - Stewart, E. J.C.
AU - Hu, J.
AU - Quigley, S. F.
AU - Chan, A. H.C.
PY - 2006
Y1 - 2006
N2 - This paper describes a study of the use of FPGA-based reconfigurable hardware, in the form of a coprocessor within a standard PC, to accelerate a solution of the 3-D finite difference formulation of the Laplace equation. The domain decomposition and solution approach are formulated so as to make maximum use of the parallelism within the FPGA, and to minimize limitations imposed by I/O bandwidth between the FPGA and the computer memory. The resulting system provides a red-black SOR solver that can achieve a speed-up of approximately 50 compared to a fast PC.
AB - This paper describes a study of the use of FPGA-based reconfigurable hardware, in the form of a coprocessor within a standard PC, to accelerate a solution of the 3-D finite difference formulation of the Laplace equation. The domain decomposition and solution approach are formulated so as to make maximum use of the parallelism within the FPGA, and to minimize limitations imposed by I/O bandwidth between the FPGA and the computer memory. The resulting system provides a red-black SOR solver that can achieve a speed-up of approximately 50 compared to a fast PC.
KW - Domain decomposition
KW - Finite difference method
KW - FPGAs
KW - Hardware acceleration
KW - Reconfigurable computing
UR - http://www.scopus.com/inward/record.url?scp=84863338804&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84863338804
SN - 1905088094
SN - 9781905088096
T3 - Proceedings of the 5th International Conference on Engineering Computational Technology
BT - Proceedings of the 5th International Conference on Engineering Computational Technology
T2 - 5th International Conference on Engineering Computational Technology, ECT 2006
Y2 - 12 September 2006 through 15 September 2006
ER -