With the diversification of HPC architectures beyond traditional CPU-based clusters, a number of new frameworks for performance portability across architectures have arisen. One way of implementing such frameworks is to use C++ templates and lambda expressions to design loop-like functions. However, lower level programming APIs that these implementations must use are often designed with C in mind and do not specify how they interact with C++ features such as lambda expressions. This paper discusses a change to the behavior of the OpenMP specification with respect to lambda expressions such that when functions generated by lambda expressions are called inside GPU regions, any pointers used in the lambda expression correctly refer to device pointers. This change has been implemented in a branch of the Clang C++ compiler and demonstrated with two representative codes. This change has also been accepted into the draft OpenMP®specification for inclusion in OpenMP 5. Our results show that the implicit mapping of lambda expressions always exhibits identical performance to an explicit mapping but without breaking the abstraction provided by the high level frameworks.
|Title of host publication
|Proceedings of LLVM-HPC 2018
|Subtitle of host publication
|5th Workshop on the LLVM Compiler Infrastructure in HPC, Held in conjunction with SC 2018: The International Conference for High Performance Computing, Networking, Storage and Analysis
|Institute of Electrical and Electronics Engineers (IEEE)
|Number of pages
|Published - 11 Feb 2019
|5th IEEE/ACM Workshop on the LLVM Compiler Infrastructure in HPC, LLVM-HPC 2018 - Dallas, United States
Duration: 12 Nov 2018 → …
|Proceedings of LLVM-HPC 2018: 5th Workshop on the LLVM Compiler Infrastructure in HPC, Held in conjunction with SC 2018: The International Conference for High Performance Computing, Networking, Storage and Analysis
|5th IEEE/ACM Workshop on the LLVM Compiler Infrastructure in HPC, LLVM-HPC 2018
|12/11/18 → …
Bibliographical noteFunding Information:
This work was completed as part of IBM’s 2017 Summer Research Internship Program. This work was also partially supported by the Centre for Computational Plasma Physics, a collaboration between the University of Warwick and the UK Atomic Weapons Establishment. Prof. Stephen Jarvis is an AWE William Penney Fellow.
© 2018 IEEE.
ASJC Scopus subject areas
- Hardware and Architecture