Parallel Implementation of K-means Algorithm on FPGA

Leonardo Dias, João Canas Ferreira, Marcelo A. C. Fernandes

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)
130 Downloads (Pure)

Abstract

The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system’s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than 15573× over a partially serial implementation.
Original languageEnglish
Article number9016001
Pages (from-to)41071-41084
Number of pages14
JournalIEEE Access
Volume8
Publication statusPublished - 27 Feb 2020

Keywords

  • FPGA
  • K-means algorithm
  • Parallel implementation
  • reconfigurable computing

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