Optimized polynomial multiplier architectures for post-quantum KEM Saber

Andrea Basso; Sujoy Sinha Roy

doi:10.1109/DAC18074.2021.9586219

Optimized polynomial multiplier architectures for post-quantum KEM Saber

Andrea Basso, Sujoy Sinha Roy

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.

Original language	English
Title of host publication	DAC '21
Subtitle of host publication	Proceedings of the 58th Annual Design Automation Conference 2021
Publisher	Association for Computing Machinery (ACM)
Pages	1285-1290
ISBN (Electronic)	978-1-6654-3274-0
ISBN (Print)	978-1-6654-3275-7
DOIs	https://doi.org/10.1109/DAC18074.2021.9586219
Publication status	Published - 8 Nov 2021
Event	Design Automation Conference - San Francisco, United States Duration: 5 Dec 2021 → 9 Dec 2021 Conference number: 58 https://www.dac.com/

Publication series

Name	DAC: Design Automation Conference
Publisher	ACM

Conference

Conference	Design Automation Conference
Abbreviated title	DAC
Country/Territory	United States
City	San Francisco
Period	5/12/21 → 9/12/21
Internet address	https://www.dac.com/

Access to Document

10.1109/DAC18074.2021.9586219Licence: None: All rights reserved

Cite this

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title = "Optimized polynomial multiplier architectures for post-quantum KEM Saber",

abstract = "Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.",

author = "Andrea Basso and {Sinha Roy}, Sujoy",

year = "2021",

month = nov,

day = "8",

doi = "10.1109/DAC18074.2021.9586219",

language = "English",

isbn = "978-1-6654-3275-7",

series = "DAC: Design Automation Conference ",

publisher = "Association for Computing Machinery (ACM)",

pages = "1285--1290",

booktitle = "DAC '21",

address = "United States",

note = "Design Automation Conference, DAC ; Conference date: 05-12-2021 Through 09-12-2021",

url = "https://www.dac.com/",

}

Basso, A & Sinha Roy, S 2021, Optimized polynomial multiplier architectures for post-quantum KEM Saber. in DAC '21: Proceedings of the 58th Annual Design Automation Conference 2021. DAC: Design Automation Conference , Association for Computing Machinery (ACM), pp. 1285-1290, Design Automation Conference, San Francisco, United States, 5/12/21. https://doi.org/10.1109/DAC18074.2021.9586219

Optimized polynomial multiplier architectures for post-quantum KEM Saber. / Basso, Andrea; Sinha Roy, Sujoy.
DAC '21: Proceedings of the 58th Annual Design Automation Conference 2021. Association for Computing Machinery (ACM), 2021. p. 1285-1290 (DAC: Design Automation Conference ).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Optimized polynomial multiplier architectures for post-quantum KEM Saber

AU - Basso, Andrea

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N1 - Conference code: 58

PY - 2021/11/8

Y1 - 2021/11/8

N2 - Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.

AB - Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.

UR - https://dl.acm.org/conference/dac/proceedings

UR - https://www.dac.com/

U2 - 10.1109/DAC18074.2021.9586219

DO - 10.1109/DAC18074.2021.9586219

M3 - Conference contribution

SN - 978-1-6654-3275-7

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SP - 1285

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BT - DAC '21

PB - Association for Computing Machinery (ACM)

T2 - Design Automation Conference

Y2 - 5 December 2021 through 9 December 2021

ER -

Optimized polynomial multiplier architectures for post-quantum KEM Saber

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Conference

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