Optimized polynomial multiplier architectures for post-quantum KEM Saber

Andrea Basso, Sujoy Sinha Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Saber is one of the four finalists in the ongoing NIST post-quantum cryptography standardization project. A significant portion of Saber's computation time is spent on computing polynomial multiplications in polynomial rings with powers-of-two moduli. We propose several optimization strategies for improving the performance of polynomial multiplier architectures for Saber, targeting different hardware platforms and diverse application goals. We propose two high-speed architectures that exploit the smallness of operand polynomials in Saber and can achieve great performance with a moderate area consumption. We also propose a lightweight multiplier that consumes only 541 LUTs and 301 FFs on a small Artix-7 FPGA.
Original languageEnglish
Title of host publicationDAC '21
Subtitle of host publicationProceedings of the 58th Annual Design Automation Conference 2021
PublisherAssociation for Computing Machinery (ACM)
ISBN (Electronic)978-1-6654-3274-0
ISBN (Print)978-1-6654-3275-7
Publication statusPublished - 8 Nov 2021
EventDesign Automation Conference - San Francisco, United States
Duration: 5 Dec 20219 Dec 2021
Conference number: 58

Publication series

NameDAC: Design Automation Conference


ConferenceDesign Automation Conference
Abbreviated titleDAC
Country/TerritoryUnited States
CitySan Francisco
Internet address


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