Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs

Xu Wang, Marta Kwiatkowska, Georgios Theodoropoulos, [No Value] [No Value]

Research output: Contribution to conference (unpublished) › Paper

4 Citations (Scopus)

Original language	English
Pages	189-206
Number of pages	18
DOIs	https://doi.org/10.1016/j.entcs.2005.05.042
Publication status	Published - 26 Jan 2006
Event	Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design (FMGALS 2005) - Duration: 26 Jan 2006 → …

Conference	Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design (FMGALS 2005)
Period	26/01/06 → …

Access to Document

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title = "Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs",

author = "Xu Wang and Marta Kwiatkowska and Georgios Theodoropoulos and \{[No Value]\}, \{[No Value]\}",

year = "2006",

month = jan,

day = "26",

doi = "10.1016/j.entcs.2005.05.042",

language = "English",

pages = "189--206",

note = "Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design (FMGALS 2005) ; Conference date: 26-01-2006",

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TY - CONF

T1 - Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs

AU - Wang, Xu

AU - Kwiatkowska, Marta

AU - Theodoropoulos, Georgios

AU - [No Value], [No Value]

PY - 2006/1/26

Y1 - 2006/1/26

UR - https://www.scopus.com/pages/publications/30644470561

U2 - 10.1016/j.entcs.2005.05.042

DO - 10.1016/j.entcs.2005.05.042

M3 - Paper

SP - 189

EP - 206

T2 - Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design (FMGALS 2005)

Y2 - 26 January 2006

ER -