Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic

Stephen Melnikoff; Steven Quigley; Martin Russell

Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic

Stephen Melnikoff, Steven Quigley, Martin Russell

Electronic, Electrical and Systems Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

354 Downloads (Pure)

Abstract

Performing Viterbi decoding for continuous real-time speech recognition is a highly computationally-demanding task, but is one which can take good advantage of a parallel processing architecture. To this end, we describe a system which uses an FPGA for the decoding and a PC for pre- and post-processing, taking advantage of the properties of this kind of programmable logic device, specifically its ability to perform in parallel the large number of additions and comparisons required. We compare the performance of the FPGA decoder to a software equivalent, and discuss issues related to this implementation.

Original language	English
Title of host publication	Field-Programmable Logic and Applications, 11th International Conference, FPL 2001. Proceedings
Publisher	Springer
Pages	81-90
Number of pages	10
Publication status	Published - 1 Jan 2001
Event	International Conference on Field-Programmable Logic and Applications - Duration: 1 Jan 2001 → …

Publication series

Name	Lecture Notes in Computer Science
Publisher	Springer Verlag
Volume	2147
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	International Conference on Field-Programmable Logic and Applications
Period	1/01/01 → …

Bibliographical note

null

The original publication is available at www.springerlink.com

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Cite this

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title = "Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic",

abstract = "Performing Viterbi decoding for continuous real-time speech recognition is a highly computationally-demanding task, but is one which can take good advantage of a parallel processing architecture. To this end, we describe a system which uses an FPGA for the decoding and a PC for pre- and post-processing, taking advantage of the properties of this kind of programmable logic device, specifically its ability to perform in parallel the large number of additions and comparisons required. We compare the performance of the FPGA decoder to a software equivalent, and discuss issues related to this implementation.",

author = "Stephen Melnikoff and Steven Quigley and Martin Russell",

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year = "2001",

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language = "English",

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Melnikoff, S, Quigley, S & Russell, M 2001, Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic. in Field-Programmable Logic and Applications, 11th International Conference, FPL 2001. Proceedings. Lecture Notes in Computer Science, vol. 2147, Springer, pp. 81-90, International Conference on Field-Programmable Logic and Applications, 1/01/01. <http://www.springerlink.com/content/u4hypwf0bnhfc76d>

Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic. / Melnikoff, Stephen; Quigley, Steven; Russell, Martin.
Field-Programmable Logic and Applications, 11th International Conference, FPL 2001. Proceedings. Springer, 2001. p. 81-90 (Lecture Notes in Computer Science; Vol. 2147).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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PY - 2001/1/1

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N2 - Performing Viterbi decoding for continuous real-time speech recognition is a highly computationally-demanding task, but is one which can take good advantage of a parallel processing architecture. To this end, we describe a system which uses an FPGA for the decoding and a PC for pre- and post-processing, taking advantage of the properties of this kind of programmable logic device, specifically its ability to perform in parallel the large number of additions and comparisons required. We compare the performance of the FPGA decoder to a software equivalent, and discuss issues related to this implementation.

AB - Performing Viterbi decoding for continuous real-time speech recognition is a highly computationally-demanding task, but is one which can take good advantage of a parallel processing architecture. To this end, we describe a system which uses an FPGA for the decoding and a PC for pre- and post-processing, taking advantage of the properties of this kind of programmable logic device, specifically its ability to perform in parallel the large number of additions and comparisons required. We compare the performance of the FPGA decoder to a software equivalent, and discuss issues related to this implementation.

M3 - Conference contribution

T3 - Lecture Notes in Computer Science

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BT - Field-Programmable Logic and Applications, 11th International Conference, FPL 2001. Proceedings

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T2 - International Conference on Field-Programmable Logic and Applications

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Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic

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