High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware

In this paper, we present an instruction set coprocessor architecture forlattice-based cryptography and implement the module lattice-based post-quantum keyencapsulation mechanism (KEM) Saber as a case study. To achieve fast computationtime, the architecture is fully implemented in hardware, including CCA transforma-tions. Since polynomial multiplication plays a performance-critical role in the moduleand ideal lattice-based public-key cryptography, a parallel polynomial multiplierarchitecture is proposed that overcomes memory access bottlenecks and results in ahighly parallel yet simple and easy-to-scale design. Such multipliers can compute afull multiplication in256cycles, but are designed to target any area/performancetrade-offs. Besides optimizing polynomial multiplication, we make important designdecisions and perform architectural optimizations to reduce the overall cycle countsas well as improve resource utilization.For the module dimension 3 (security comparable to AES-192), the coprocessorcomputes CCA key generation, encapsulation, and decapsulation in only 5,453, 6,618and 8,034 cycles respectively, making it the fastest hardware implementation of Saberto our knowledge. On a Xilinx UltraScale+ XCZU9EG-2FFVB1156 FPGA, theentire instruction set coprocessor architecture runs at 250 MHz clock frequency andconsumes 23,686 LUTs, 9,805 FFs, and 2 BRAM tiles (including 5,113 LUTs and3,068 FFs for the Keccak core).