Fully parallel proposal of Naive Bayes on FPGA

Wysterlânya K. P. Barros, Matheus T. Barbosa, Leonardo A. Dias, Marcelo A. C. Fernandes

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This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gate Array (FPGA) is presented and evaluated regarding the hardware area occupation, processing time (throughput), and dynamic power consumption. In addition, a comparative design analysis was carried out with state-of-the-art works, showing that the proposed implementation achieved a speedup of up to 104× and power savings of up to 107×-times while also reducing the hardware occupancy by up to 102×-times fewer logic cells.
Original languageEnglish
Article number2565
Pages (from-to)2565
Number of pages15
Issue number16
Publication statusPublished - 17 Aug 2022


  • FPGA
  • Hardware
  • Machine Learning
  • Naive Bayes
  • Parallel implementation


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