An Intergrated Framework for Formal Vertification and Distributed Simulation of Asynchronous

Theodoropoulos, Georgios (Principal Investigator)
Kwiatkowska, Marta (Co-Investigator)

Computer Science

2 Paper

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2006

Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs
Wang, X., Kwiatkowska, M., Theodoropoulos, G. & [No Value], N. V., 26 Jan 2006, p. 189-206. 18 p.
Research output: Contribution to conference (unpublished) › Paper

4 Citations (Scopus)
2005

Towards a unifying CSP approach for hierarchical verification of asynchronous hardware. In Proceedings of 4th Workshop on Automated Verification of Critical Systems (AVoCS '04)
Wang, X., Kwiatkowska, M., Theodoropoulos, G. & Zhang, Q., 23 May 2005, p. 231-246. 16 p.
Research output: Contribution to conference (unpublished) › Paper

8 Citations (Scopus)